High input impedance circuit for a field effect transistor including capacitive gate biasing means



Jan. 27, 1970 R. H. CRAWFORD 3, HIGH INPUT IMPEDANCE CIRCUIT FOR A FIELDEFFECT TRANSISTOR INCLUDING CAPACITIVE GATE BIASING MEANS Filed Dec. 22,1966 2 Sheets-Sheet 1 INVENTOR Roberr H. Crawford Jam 1 7 R. H. CRAWFORD3,492,511

HIGH INPUT PE CE CIRC FOR A FIELD EFFECT- TRANSISTOR LU G CAPAC VE GATEBIASING MEANS Filed Dec. 22, 1966 2 Sheets-Sheet 2 GATE United StatesPatent 3,492,511 HIGH INPUT IMPEDANCE CIRCUIT FOR A FIELD EFFECTTRANSISTOR INCLUDING CAPACITIVE GATE BIASING MEANS Robert H. Crawford,Richardson, Tex., assignor to Texas Instruments Incorporated, Dallas,Tex., a corporation of Delaware Filed Dec. 22, 1966, Ser. No. 604,033Int. Cl. H03k 3/26 U.S. Cl. 307304 4 Claims ABSTRACT OF THE DISCLOSUREThis invention relates to a gate circuit for an insulated gate fieldeffect transistor wherein a biasing capacitor is placed in seriesbetween the internal capacitance of the gate, the biasing voltage, andthe source so that the internal capacitance of the gate and thecapacitance of the biasing capacitor determine the voltage drop betweenthe gate and the source. The circuit thus provides a high inputimpedance to a signal applied thereto. The biasing capacitor may bemanufactured on the same chip as the insulated gate field effecttransistor.

This invention relates to metal-oxide-semiconductor field-effecttransistors, and more particularly to a capacitor-biasing of suchtransistors.

The metal-oxide-semiconductor field-effect transistor (MOS-FET) is avoltage control device that exhibits an extremely high input resistance(in the range of about to 10 ohms). Unlike the junction field-effecttransistor, the MOS transistor with its insulated gate maintains a highinput resistance without regard to the magnitude of the input gatevoltage.

A typical P-channel MOS-PET has two highly doped P conductivity-typeregions which are formed in an N conductivity-type silicon substrate.These two regions are referred to as the source and drain, and arelocated in close proximity to each other. Approximately 0.2 millinchseparation is commonly used for a driver device and 12 millinches ofseparation for a load device. A thin layer (8002000 A.) of insualtingmaterial, usually some form of silicon oxide, is formed on the surfaceof the silicon substrate, the oxide on the substrate surface between thesource and drain forming the gate dielectric. A metal layer isevaporated on the surface of the oxide layer including the surfacebetween the source and drain. The metal layer is covered with a mask ofphotoresist material and subjected to an etching condition for a periodof time sufficient to define the source and drain contacts,interconnecting leads and the gate electrode (metal layer on the surfaceof the oxide between the source and drain) of the MOS-PET.

Because of the conditions created by the interface of the siliconsubstrate and oxide layer, most N-channel devices are initially on (atzero gate bias) while all P-channel devices are initially off. Since itis desirable to use an initially off device for switching and digitalcircuits, most commercial MOS-FETs at the present time are singlepolarity P-channel devices.

With the drain and source grounded, the gate controls the charge in thechannel (the region near the substrate surface between the source andthe drain). A negative bias applied to the gate modifies the conditionswithin the silicon between the source and drain. As the gate develops anegative charge, free electrons present in the N conductivity-typesilicon are repelled, forming a depletion region. Once sufficientdepletion has occurred, additional gate bias attracts positive mobileholes to the surface. When enough holes have accumulated in the channelarea, the surface of the silicon changes from electron dominated to holedominated material and is said to have become inverted. Thus thesituation now exists where the two P conductivity-type regions areconnected together by a P- conductivity type inversion layer or channel(hence the nomenclature P-channel device). A signal on the gatemodulates the number of carriers within the channel region so that thegate, in effect, controls current flowing in the channel.

The normal biasing method for MOS-FETs is to apply a voltage to the gateby a resistor network. Due to the high resistance between the gate andsource it is desirable to have the biasing resistor extremely high inresistance, being in the meg-ohm range. However, suitable resistors ofthis magnitude are difficult to manufacture in small sizes and with goodaccuracies. Also, in certain applications where high input impedance isimportant, such as in computer memory systems where information isstored by a charge on a capacitor and operational amplifiers, aresistance network is detrimental due to a low input impedance.

It is therefore an object of the invention to provide a biasingarrangement for biasing a MOS-PET by the use of a biasing capacitor.

The novel features believed to be characteristic of this invention areset forth with particularly in the appended claims. This inventionitself, however, as well as further objects and advantages thereof maybest be understood by reference to the following detailed descriptionwhen read in conjunction wtih the accompanying drawings, wherein:

FIGURE 1 is a schematic diagram of a MOS-PET;

FIGURE 2 is a graph of a family of drain current vs. drain-to-sourcevoltage curves at different gate voltages for a typical MOS-PET;

FIGURE 3 is a sectional view of a typical P-channel MOS-PET;

FIGURE 4 is a schematic diagram illustrating an equivalent input circuitof a typical MOS-PET at low input frequencies;

FIGURE 5a is a schematic diagram illustrating a MOS- FET with acapacitor biasing arrangement;

FIGURE 5b is a schematic diagram illustrating the equivalent circuit ofthe MOS-PET circuit shown in FIG- URE 501;

FIGURE 6 is a sectional view of a portion of a monolithic integratedcircuit illustrating a substrate containing a MOS-PET with a biasingcapacitor on the surface of the substrate;

FIGURE 7 is a schematic diagram illustrating a capacitor biased MOS-FETused as the input stage of a high voltage electrometer-type circuit.

Briefly, a biasing capacitor is placed in the gate circuit such that itis in series with the internal capacitance of the gate (the internalcapacitance is formed by the oxide layer between the gate and thesource) and a biasing voltage. Since the internal resistance between thegate and source is high in relationship to the internal capacitancebetween the gate and source at the instant the bias voltage is applied,the effect of the internal resistance can be neglected at this point intime and the voltage drop between the gate and source (input voltage) iscontrolled essentially by the internal capacitance and the biasingcapacitor. After said capacitance and said capacitor are charged, thevoltage of the capacitors decreases due to the current leakage betweenthe plates of each capacitor so that the resistance of each capacitorthen determines the voltage drop across each capacitor.

As seen by the equations:

where V is the voltage input or the voltage between the gate and source.V is the voltage across both the biasing capacitor and the capacitorformed between the gate and source, C and R are the internal capacitanceand resistance, respectively, between the gate and the source, while Cand R are the capacitance and resistance, respectively, of the biasingcapacitor. The voltage input is then the effective gate bias for theMOSFET. The input voltage may be varied by varying the Vbias or C (C,being fixed by the geometry of the MOS-FET).

The operation of a MOSFET can best be explained by first referring toFIGURE 1 which is a schematic diagram of such a device. A MOS-FETcomprises a gate 1, a drain 2 and a source 3. Point 4, which is thesubstrate itself, is sometimes called a back gate and is usuallyconnected in common to the source. Source 3 is usually at groundpotential while the drain 2 is at a negative potential. The gate 1potential is negative also and is of such a value as to lie betweenground and the drain voltage.

FIGURE 2 is a graph of drain current I versus drain voltage V curves atdifferent gate biasing voltages V of a typical MOSFET. The drain currentI at a constant drain voltage is controlled by the gate bias V with thedrain current I increasing in magnitude with an increase of the gatebias V in a negative direction.

A MOS-FET, as shown in FIGURE 3, is formed by diffusing into an Nconductivity-type silicon substrate 5, for example, a P+conductivity-type source 3 and P+ conductivity-type drain 2 which areseparated from each other by a region 6 which is a portion of the Nconductivity-type substrate of between about 0.2 millinch to about 2millinches in thickness. A protective layer of ma terial 7, for examplesilicon oxide, is formed on the surface 8 of the substrate 5 withwindows exposing portions of the P+ conductivity-type source 3 and theP+ conductivity-type drain 2. Metal contacts are then formed on thesilicon oxide 7 and the exposed portions of the source 3 and drain 2 toform the source contact 9, the gate 1 and the drain contact 10.

A MOSFET operates in the enhancement mode which is easily explained bythe following sequence of events, referring once again to FIGURE 3. Asthe gate 1 becomes more negatively biased in relationship to the source3, a depletion layer 11 is formed along the sourcesubstrate junction,the drain-substrate junction and along the area directly beneath thegate 1. The bias voltage is increased negatively until the thresholdvoltage is reached, at which time the area directly beneath the gateinverts to a P type region 12 and enables the MOSFET to operate in whatis called the enhancement mode.

The equivalent input circuit of a MOSFET is shown in FIGURE 4. The inputimpedance Z is formed by the effect of the internal capacitance C andthe internal resistance R between the gate and the source. Typicalvalues of R are to 10 ohms and of C are 0.1 pf. to l pf. The internalcapacitance (gate capacitance) is always present, for the gate must beseparated from the 4 substrate by a layer of oxide for the MOSFET tooperate. The effective bias voltage is the voltage which appears acrossC Normally, this bias is applied to the gate through a resistor network.

By using an external capacitor to control the voltage drop between thesource and gate, the correct bias can be established to a MOS-FETwithout using a biasing resistor. In FIGURE 5a there is illustrated aschematic diagram of a MOSFET with a capacitor biasing arrangement.FIGURE 5b illustrates the equivalent circuit of the actual circuit shownin FIGURE 5a.

The biasing voltage V is across the biasing capacitor C and the internalresistance R and internal capacitance C between the gate and source. Theback plate or substrate is connected in common to the source. The inputvoltage V is the voltage drop between the gate and source and thusfurnishes the necessary biasing action.

The biasing capacitor 20 (FIGURE 6) can be fabricated on the substratecontaining the MOSFET whether the transistor is a discrete device or oneamong many other components of an integrated circuit, as seen in FIGURE6. The biasing capacitor 20 is formed by conventional thin filmtechniques on the surface 21 of the N conductivity type siliconsubstrate 22. The biasing voltage is applied at terminal 23 to thebottom plate 24 of the biasing capacitor 20, while the top plate 25 ofthe capacitor 20 is connected to the gate 1 by conductor 30. The sourceterminal 26 makes contact to the source 3 and substrate 22 (back gate)while the drain terminal 27 makes contact to the drain 2. The voltagedrop between the gate 1 and the source 3 biases the MOSFET.

One application for a capacitor biased MOSFET is a high-voltage inputstage for an electrometer circuit. The arrangement of the input stage ofsuch a circuit is shown in FIGURE 7 with a voltage V higher than cannormally be applied to an MOS-FET by itself, applied to the input 29 ofthe circuit. (V may be in the order of to 300 volts). This voltage Vbiasis divided down by the capacitive voltage divider circuit formed bycapacitor C and the internal capacitance C of the MOSFET. The inputvoltage that appears across C biases the MOSFET. The value of this inputvoltage is set by the ratio of C and C and is much lower than V Theoutput V of the circuit is measured at the drain terminal 30.

The above described capacitor biased MOS-FET has an advantage over aMOS-PET whose gate oxide is made thick enough to withstand the fullbiasing voltage V This advantage is illustrated in the circuit schematicshown in FIGURE 7. The MOS-FET is designed to operate with an inputvoltage in the range of 4 to 10 volts. To calibrate the inputelectrometer-type circuit shown above it is necessary to observe theoutput while a known voltage standard V is applied to the MOS- FET gateby the switch S which has one terminal connected to the referencevoltage V and a second terminal connected to the biasing capacitor C Avoltage reference in the order of 5 to 6 volts can be used. This is inthe range of temperature compensating Zener diodes. If the gate oxide ofthe MOS-FET is made thick enough to withstand all the biasing voltage Vthen the reference voltage V would have to be of the same order (100-300volts). This higher voltage is more diflicult to achieve than a 5 voltreference source. A second advantage the invention has over a MOS-FETwithout capacitor bias is the fact that a number of capacitors (C can befabricated on the same chip with leads brought out to an externalswitch. Thus by varying the value of C the voltage scale of the circuitis changed.

Various modifications of the invention will become apparent to personsskilled in the art without departing from the spirit and scope of theinvention as defined by the appended claims.

What is claimed is:

1. A high input impedance gate circuit for an insulated gate fieldefiect transistor comprising:

(a) an insulated gate field effect transistor including a drain, asource, and a gate, said source and said gate having an internalcapacitance between them,

(b) a nonpolar biasing capacitor means connected in series with saidgate,

(c) voltage means connected to said source and said biasing capacitormeans for providing a biasing voltage across said biasing capacitormeans and cross said source and gate internal capacitance, said biasingcapacitor means together with said source and gate capacitance beingmeans for controlling the voltage drop between said source and gate andproviding a high input impedance to an input signal applied to said gateof the transistor.

2. A circuit as recited in claim 1 wherein said insulated gate fieldeffect transistor and said biasing capacitor means are formed on acommon substrate.

3. A circuit as recited in claim 2 wherein said insulated gate fieldeffect transistor is a P-channel device operating in the enhancementmode and the substrate is of N conductivity type silicon.

4. An electrometer circuit comprising:

(a) an insulated gate field efiect transistor having a source, a gate,and a drain, said source and gate having an internal capacitance, saiddrain providing a voltage signal output and said source being connectedto ground,

(b) a nonpolar biasing capacitor means connected to said gate,

(c) a biasing voltage source connected in series with said biasingcapacitor means and .(d) means for connecting a voltage source to bemeasured to the gate of said transistor, said biasing capacitor meanstogether with said source and gate internal capacitance providing avoltage divider for determining the potential of an input voltage sourceconnected to said gate.

References Cited UNITED STATES PATENTS 3,325,654 6/1967 Mrazek 3073033,343,049 9/1967 Miller et al 317234 3,138,744 6/1964 Kilby 317235 X3,202,840 8/1965 Ames 317235 X 3,296,508 1/1967 Hofstein 3172353,313,959 4/1967 Dill 317-235 X 3,356,858 12/1967 Wanlass 317235 X JAMESD. KALLAM, Primary Examiner US. Cl. X.R. 317-235, 238

